1. Field of the Invention
The present invention relates to a parasitic MIM (metal/insulator/metal) structural spot analysis method for a semiconductor device and a parasitic MIM structural spot analysis method for a Si semiconductor device, which are suitable for inspections of failures of wirings on a semiconductor integrated circuit chip and for inspection of failures of a wiring system such as vias and contact holes.
2. Description of the Related Art
For a conventional failure detection and analysis method for a semiconductor device such as a semiconductor integrated circuit, which is an object of the present invention, there have been, for example, Japanese Patent Application Laid Open No. 6-300824 (hereinafter, referred to as reference 1), Nikawa, K., C. Matsumoto, and S. Inoue, "Verification and Improvement of the Optical Beam Induced Resistance Variation (OBIRCH) method", Proc. International Symposium for testing and Failure Analysis, pp. 11-16 (1994) (hereinafter, referred to as reference 2) (both references 1 and 2 are hereinafter referred to as prior art 1), Koyama, T., Mashiko, M. Sekine, H. Koyama and K. Horie, "New non-bias optical beam induced current technique for evaluation of Al interconnects", Proc. IRPS, pp. 228-233 (1995) (hereinafter, referred to as reference 3), and Mashiko, Y., T. Koyama, and H. Koyama, Proc. 6th European Symp. Rel. Electron Devices, Failure Phys. And Analysis, pp 293-298 (1995) (hereinafter, referred to as reference 4) (both references 3 and 4 are hereinafter referred to as prior art 2).
Apparatuses of prior art 1 and 2 have a common constitution. FIG. 1 shows a constitution of an inspection apparatus for a semiconductor device disclosed in these references. On a sample stage 111 an integrated circuit 116 is mounted as a sample. Laser beam 119 emitted from a laser beam generation section 113 is incident on a microscope section 114, and is irradiated onto a chip of the integrated circuit 116 after being converged. A constant power source 115, a current variation detection section 117 and a test pattern generation section 118 are connected to the sample stage 111. The test pattern generation section 118 serves to generate test patterns for setting the integrated circuit 116 to a specific state, onto which the laser beam 119 is irradiated. The constant power source 115, the current variation detection section 117 and the test pattern generation section 118, which are connected to the sample stage 111, are electrically connected to corresponding pins of the integrated circuit 116.
The microscope section 114, the constant power source 115, the current variation detection section 117 and the test pattern generation section 118 are connected to a system controlling/signal processing section 121 for controlling the whole system and for processing an acquired signal. The system controlling/signal processing section 121 is designed so as to perform a predetermined control operation and signal processing. An image display section 122 is formed of a CRT, which is connected to the system controlling/signal processing section 121. The image display section 122 is designed such that an image as a result of processing of the acquired signal is displayed thereon.
According to the prior failure detection/analysis method for a semiconductor device, the laser beam is irradiated onto a region of the integrated circuit 116 to be detected while scanning the laser beam thereon. Then, an increase in resistance which is caused by an increase in temperature due to an increase in the irradiation light (the prior art 1), and a generation of a thermally generated emf (the prior art 2) are detected as a current variation using the current variation detection section 117. Subsequently, for example, in synchronization with scanning of the light beam 119, variations in the current flowing through the wiring to be detected are displayed on the image display section 122 in the form of variations in luminance or in the form of pseudo colors which are obtained by converting the luminance thereto for convenience, the variations corresponding to every irradiated position. Thus, detection of a void more than 0.1 .mu.m in the wiring (the reference 2), a void more than 0.5 .mu.m in the wiring (the reference 3) and a parasitic interposition layer of about 50 nm between a via and a wiring (the reference 4) are possible.
A principle for detecting them will be briefly described. First, a principle of the prior art 1 will be described. It is assumed that a variation in a current due to a temperature increase at the time of irradiation of beam onto the portion of a wiring in an integrated circuit is .DELTA.I. Assuming that a constant voltage is applied to opposite ends of the wiring and the system is connected in series to the wiring, the variation .DELTA.I in the current is approximated by the following equation (1), EQU .DELTA.I.apprxeq.-(.DELTA.R/R)I (1)
where R is a resistance obtained by summing up the resistance of the wiring and the resistance of the system connected in series to the wiring, at the time when no beam is irradiated thereon, and .DELTA.R is a variation of the resistance of the wiring due to the beam irradiation. Moreover, I is a current flowing through the wiring at the time when no beam is irradiated.
Since the resistance R is constant if the wiring to be observed and the system connected in series thereto are decided, the product of the variation .DELTA.R of the resistance and the current I can be obtained by measuring the variation .DELTA.I of the current, as long as other conditions are kept constant. Moreover, when the current I is made constant, the rate of variation .DELTA.R of the resistance in each portion of the wiring can be detected. Detailed description about it will be made as follows.
This is disclosed in the references 1 and 2 as a detection method of defects such as voids and Si precipitation. Specifically, if beam conditions, materials of the irradiated portions and shapes are the same, the ratios of variation .DELTA.R of the resistance in each portion differ only depending on a thermal conductivity thereof. If there are defects such as voids and Si precipitation in the wiring, the thermal conductivity differs. It has been experimentally confirmed that the difference of the ratio of variation .DELTA.R of resistance can be observed by virtue of this effect. Since the voids and Si precipitation in the wiring are important as factors to decide reliability of the integrated circuit, this effect has importance. For sizes of the voids to be detected according to this method, the ones having the minimum size of 0.1 .mu.m are disclosed in the reference 2. At this time, in order to verify the existence of voids of about 0.1 .mu.m, an SIM (scanning type ion microscope) is used. This method is called an OBIRCH method (an Optical Beam Induced Resistance Change method).
Effectiveness of a method called a NB-OBIC method (a Non-Bias Optical Beam Induced Current method) (the prior art 2) utilizing a thermoelectric effect by laser beam heating on detection of failures such as voids of the wiring system (the reference 3) is also disclosed as a method using beam heating. This NB-OBIC method differs from the OBIRCH method only in that no voltage need be applied to the integrated circuit to be observed, and others are the same as the OBIRCH method. It should be noted that the NB-OBIC method described later can not be principally used for observation of the current unlike the OBIRCH method. The principle of the NB-OBIC method is explained as follows. Specifically, when defects exist in the wiring system, the thermal conductivity of the portions of the defects differs from the positions other than the defects. Or, the thermal conductivity state differs because of existence of the defects. Therefore, a temperature gradient is produced, resulting in production of thermally generated emf. The thermally generated emf is detected as the current. It has been disclosed in the reference 3 that the minimum size of the void to be detected according to this method is about 0.5 .mu.m. In order to verify the existence of the voids of about 0.5 .mu.m, the SEM (Scanning Electron Microscope) has been used.
Moreover, it has been disclosed in the reference 4 that by applying some quantity of a voltage (0.23 V), a parasitic interposition layer of about 50 nm thick can be detected under the via according to this principle. At this time, the SEM (Scanning Electron Microscope) has been used also in order to verify existence of a parasitic interposition layer of about 50 nm thick.
FIG. 2 is an explanatory view for explaining the principle concept of a method to detect defects by the above-described prior arts 1 and 2.
For the simplicity of explanation, a Si substrate and an insulating film such as a cover insulating film, an interlayer insulating film and a base oxide film are omitted. In the prior arts 1 and 2, the void 508 which is located on the interlayer insulating film 201 and at the bottom of the wiring 102 can be detected, and the size thereof is 0.1 .mu.m or more as described above.
Moreover, the parasitic interposition layer 507 can be detected using the prior art 2, and the thickness thereof is 50 nm or more as described above. The detection method of the parasitic interposition layer 507 is as follows. It is assumed that laser beam 504 is irradiated onto a metal wiring 102 which is a second layer of a semiconductor device and, in some cases, the laser beam 504 is scanned in the direction of the arrow 123 shown by a broken line. In cases where the current 112 flows through the wiring 102, the via 103 and the wiring 101, the irradiation of the laser beam 504 increases the temperature of the parasitic interposition layer 507, resulting in an increase in the current flowing through the parasitic interposition layer 507 due to a temperature characteristic of the layer 507. Therefore, by detecting the variation .DELTA.I of the current, the portions of the parasitic interposition layer structure produced on the semiconductor device can be detected.
There has been the following problem in the conventional abnormality detection method for the semiconductor device and the apparatus of the same as described above. This problem is an obstacle to the application of this method to the analysis with a high sensitivity for the wiring system.
(1) The minimum size of the void capable of being detected when using the prior art is about 0.1 .mu.m, and the minimum thickness of the parasitic interposition layer under the via is about 50 nm, as described above. In actual failure prone products, a thin insulating film less than 10 nm is produced at the interface between the via and the wiring, and there is the problem that a phenomenon occurs which leads to resistance abnormality which affects device characteristics.
Analysis of such thin film is impossible without a TEM (Transmission Electron Microscope). Moreover, since there is no way to know in which vias estimated to be electrically failure-prone, whether such thin insulating films exist. It has been possible to analyze the portions (parasitic MIM structural spots) of the interface between the via and the wiring where the thin insulating film less than 10 nm is produced using the TEM, but only when the sample is prepared under extreme conditions such that the insulating films exist either all over the range to be electrically observed or in all vias.
(2) Current Si devices having two or three levels are not unusual, and devices of multilevel structure composed of four levels or more have been launched. In such multilevel wiring structures, the wiring located in the upper portion of the device has a wider width than the wiring located at the lower portion. The observation of the wiring system located in the lower level portion is more difficult when the observation is performed from the chip surface.
(3) Moreover, when the analysis is performed after mounting, in the situation where most of the surface of the chip is covered with leads like a LOD (Lead On Chip) package, observation of the whole chip is very difficult from the surface of the chip. Moreover, in the situation where the surface of the chip is thoroughly covered with a ceramic substrate and the like, observation from the surface of the chip is very difficult.